Jobs at Blue Origin

Design and layout complex multi-layer PCBs for mmWave/RF, high-speed digital, mixed-signal, and high-power systems. Perform stackup and routability studies, signal integrity analysis, create DRCs and fabrication/assembly documentation, work with fabricators/CMs, support board bring-up and space-environment design considerations.

Lead architecture, design, integration, and validation of spacecraft TT&C communications systems. Drive RF link budgets, system requirements, ground-space integration, system-level analysis, testing, and launch readiness. Mentor a multidisciplinary team, troubleshoot RF/communications anomalies, coordinate cross-functional teams, and support regulatory/licensing and verification activities.

Build Blue Origin’s pre-silicon emulation and FPGA prototyping capability from the ground up. Define platform strategy, select hardware, develop build and release flows, and operate nightly image services. Lead FPGA implementation, RTL adaptation, timing closure, hardware-in-the-loop integration, platform debugging, capacity planning, and user support. Collaborate with DSP, RF, antenna, verification, and architecture teams to validate satellite communications hardware and scaled beamforming datapaths.

Design and develop multithreaded embedded C/C++ software for Linux, RTOS, and bare-metal platforms supporting satellite RF, antenna, and optical systems. Develop device drivers and control, management, and data-plane functions; integrate software with hardware; debug using telemetry and hardware tools; and contribute to documentation, reviews, testing automation, CI/CD, and TDD. Lead development efforts, mentor junior engineers, and collaborate across teams to deliver reliable, high-performance space communications software.

Design and develop multithreaded embedded software in C/C++ for Linux, RTOS, and bare-metal platforms supporting satellite RF, antenna, and optical systems. Build drivers and control/data-plane functions, integrate software with hardware, debug using telemetry and hardware tools, and promote CI/CD, automated testing, and TDD practices. Provide architectural direction, participate in reviews and documentation, collaborate cross-functionally, and mentor junior engineers.

Lead architecture, design, integration, and optimization of multithreaded embedded C/C++ software for Linux, RTOS, and bare-metal platforms supporting satellite communications. Define scalability, fault-tolerance, recovery, performance, and testing strategies; troubleshoot hardware and software; guide cross-functional technical decisions; and mentor senior engineers while delivering high-quality software for space and ground systems.

Develop and operate machine learning systems for automated manufacturing. Responsibilities include building scalable data and model infrastructure, automating ML pipelines, deploying models to production and edge devices, monitoring performance, optimizing latency, integrating AI/ML tools, managing incidents, ensuring security and privacy, and collaborating with automation engineers, data scientists, data engineers, and software teams.

Develop low-level firmware for secure enclaves in custom ASICs supporting secure boot, attestation, root of trust, provisioning, secure updates, recovery, telemetry, tamper monitoring, and debugging. Collaborate with ASIC, hardware, security, software, and systems teams on interfaces and requirements. Support pre-silicon validation, FPGA and simulation development, silicon bring-up, production deployment, testing, code reviews, and documentation.

Develop ROM code and runtime firmware for digital beamforming ASICs in the TeraWave satellite communications system. Responsibilities include beam pointing, calibration, FEIC and SerDes management, secure boot, telemetry, and sideband control. The engineer will define hardware interfaces, support pre-silicon integration and validation, and conduct post-silicon ASIC bring-up and debugging. The role also involves embedded firmware and hardware interaction validation, with opportunities to lead and mentor engineers.

Develop ROM code, bootloaders, and runtime firmware for secure enclaves in custom ASICs supporting secure boot, attestation, OTA updates, provisioning, telemetry, recovery, and tamper monitoring. Collaborate with hardware and communications engineers on interfaces, pre-silicon development, integration, and validation. Support post-silicon ASIC bring-up, debugging, and embedded firmware validation.

Leads mechanical design and packaging for phased array antennas and RF payload hardware in Blue Origin’s TeraWave satellite communications network. Responsibilities include thermal management, structural and thermal analysis, tolerance stack-ups, architecture trade studies, supplier and manufacturing partner coordination, cross-program integration, and mentoring engineers. The role requires mechanical engineering expertise in complex electronic hardware, CAD modeling, finite element analysis, GD&T, and space-qualified RF systems.

Architect and build highly available control-plane network services for TeraWave’s satellite communications network. Design microservices for subscriber provisioning and session management, develop stateful distributed systems across terrestrial data centers and orbital nodes, and optimize SQL, NoSQL, and time-series databases handling billions of telemetry points. The role also involves cloud-native Kubernetes deployments, service mesh, resiliency patterns, event-driven architecture, and large-scale observability.

Own signal and power integrity for RF/mixed-signal and mmWave IC packaging. Perform HFSS and EM simulation for high-speed signals and PDNs, model and characterize RF/mmWave packages, collaborate with RFIC/mmWave/ASIC/SoC and package layout teams, lead SI/PI package delivery, and produce documentation and specifications supporting design reviews.

Design and develop RFICs and mixed-signal ASICs using Cadence Virtuoso and Spectre RF. Build analog models and verification methodologies, create and execute pre/post-silicon test plans, trade off noise/linearity/power, support lab integration and troubleshooting, resolve layout and timing issues, collaborate with systems/firmware/architecture teams, and adopt AI-based methods across design, simulation, verification, characterization, and manufacturing.

Lead verification of modem PHY IP: define strategies, build block/subsystem verification environments, create testbenches and coverage, correlate RTL with reference models, debug RTL and integration issues, support emulation/FPGA/prototyping and post-silicon debug, and drive regression automation and CI for high-throughput wireless ASIC platforms.

Lead design and development of modem PHY IP for Terawave ASIC and prototypes. Translate algorithms into hardware architectures, build bit-accurate models, perform trade studies, define interfaces, support FPGA/silicon bring-up, collaborate with systems/ASIC/RF/verification teams, and analyze simulation/emulation/lab/silicon data to improve PHY performance and validation.

Contribute to ASIC and SoC digital-block design and verification using Verilog, SystemVerilog, and UVM. Support test planning, coverage closure, assertions, protocol monitors, scoreboards, CDC/RDC/LINT checks, external IP integration, formal verification, and RTL/testbench debugging. Document design intent and verification results while collaborating with senior engineers. The role is intended for early-career engineers with relevant electrical or computer engineering education and project or coursework experience.

Lead end-to-end hardware architecture for a phased-array satellite user terminal: define system block diagrams, select SoCs and high-speed components, resolve RF/electrical/mechanical interfaces, design power/thermal systems for beamforming, drive manufacturability with CMs, and establish validation and global compliance (FCC/CE/ETSI).

Lead design and development of user terminal hardware for a high-capacity satellite network. Integrate high-speed digital logic with phased-array antennas, design HDI PCBs and power delivery, route high-speed buses (PCIe/Ethernet/MIPI/SerDes), perform EMI/noise simulations, and own hardware bring-up, debugging, and system-level testing through product lifecycle.

Design and verify complex ASICs and SoCs for TeraWave satellite communications. Responsibilities include Verilog/SystemVerilog development, subsystem and top-level integration, formal and functional verification, DSP and modem implementation, ARM and interface integration, timing constraints, FPGA flows, post-silicon bring-up, and support for DFT, LEC, floorplanning, and STA. The role requires close collaboration across front-end, back-end, software, and system teams.