As a Senior Staff Physical Design Engineer, you'll oversee ASIC design processes from RTL to GDSII, ensuring high-quality delivery and optimizing design flows in a startup environment.
Join the leading chiplet startup! As an Eliyan Sr Staff / Principal Physical Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will drive the development of cutting-edge ASICs from RTL to GDSII. You will work with a cross-functional team of industry experts that operate from first principles, innovate, and push the envelope to create high-volume and high-performance manufacturable products. In this role, you will oversee and optimize the entire design flow, including synthesis, place-and-route (PNR), static timing analysis (STA), electromigration/IR drop analysis (EM/IR), and physical verification (PV – DRC, LVS, Antenna). You will also focus on developing and improving design flows and methodologies to ensure high-quality, on-time delivery. We offer a fun work environment with excellent benefits.
Key Responsibilities:
- Define and execute block and partition physical design strategy for multiple projects, ensuring alignment with company goals and timelines.
- Drive continuous improvements in flow efficiency, automation, and quality metrics to meet power, performance, and area (PPA) targets.
- Handle the complete ASIC physical design process for blocks or partitions, from RTL handoff to GDSII delivery.
- Develop, optimize, and maintain ASIC design flow and block specific customizations for synthesis, PNR, EM/IR analysis, STA, and PV.
- Collaborate with front-end design teams on RTL, static timing design constraints, and design-for-test (DFT) collaterals.
- Drive floor planning, placement, clock tree synthesis (CTS), routing, and physical optimization in PNR.
- Perform EMIR analysis, timing closure through STA, and physical verification, including fill, DRC, LVS, and antenna checks.
- Ensure successful tapeout with full sign-off criteria met, including reliability and manufacturability requirements.
- Work closely with cross-functional teams, including front-end design, DFT, package engineering, and manufacturing.
- Present project updates and status reports to executive leadership.
Minimum Qualifications:
- Expertise in multiple areas of physical design, timing, and signoff for large, medium, and small ASICs.
- Specific experience in mixed signal SOC physical design and standard PHY implementation like D2D, PCIe, multi-gig SerDes etc.
- Strong scripting and automation skills – Tcl, Python, Makefiles.
- Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field.
Ideal Qualification:
- 8-12 years of experience in ASIC physical design, with a proven track record of leading junior engineers through successful tapeouts.
- Deep expertise in the following areas:
- Strong knowledge of EDA tools (Synopsys or Cadence) and scripting (Python, Perl).
- Exceptional problem-solving skills.
- RTL-to-GDSII flows
- Synthesis, PnR, STA, EM/IR, and PV
- Physical design for advanced process node (5nm and below) across two or more foundries
Top Skills
Asic
Cadence
Eda Tools
Em/Ir
Gdsii
Pnr
Pv
Python
Rtl
Sta
Synopsys
Tcl
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