Jobs at Intel

Design and execute mixed-signal presilicon verification plans, build testbenches and behavioral models, debug and root-cause presilicon issues, collaborate with digital/analog architects and RTL/physical design teams, and improve verification infrastructure using scripting and AI-based tools.

The role involves mixed-signal design engineering focusing on timing analysis, circuit design using Cadence ADE, and verification methodologies.

The Modeling Development Engineer will integrate and validate software for microcontroller firmware and silicon models, leveraging expertise in silicon design and modeling development practices.

Lead design and validation of analog circuits for high-speed SerDes applications, guiding junior engineers, and collaborating across functions. Requires extensive experience in analog/mixed-signal design.

Design and develop analog circuits for high-speed SerDes applications, optimizing performance, testing designs, and mentoring engineers. Collaborate across teams to ensure designs meet specifications and drive technical direction.

Design, implement, test, and maintain Triton compiler front-end and back-end components for Intel GPUs. Develop code generation and optimization passes for AI kernels, collaborate with hardware teams and compiler partners, participate in language/standards groups, and support community adoption and releases.

The Compiler Engineer will design, develop, and maintain Intel's LLVM-based compiler stack, collaborating with hardware teams and contributing to Clang and SYCL technologies, ensuring optimal compiler performance for AI and HPC applications.

The Senior Verification Engineer will lead ASIC design verification efforts, develop verification strategies, create test plans, and mentor junior engineers while ensuring coverage compliance.

Lead and execute post-silicon functional validation for SerDes IP: develop validation strategies, design test plans and infrastructure, debug mixed-signal issues, perform root-cause analysis, document results, and collaborate with architecture, design, board, platform, and manufacturing teams to optimize validation and failure resolution.