Teams at Intel

Lead and execute post-silicon functional validation for SerDes IP: develop validation strategies, design test plans and infrastructure, debug mixed-signal issues, perform root-cause analysis, document results, and collaborate with architecture, design, board, platform, and manufacturing teams to optimize validation and failure resolution.

Lead and scale Intel's compiler strategy and teams, driving multi-year direction for MLIR/LLVM-based compilers, AI/ML optimizations, and heterogeneous CPU/GPU/accelerator toolchains. Influence architecture and cross-functional roadmaps, deliver large cross-organizational programs, contribute to open-source standards, and represent Intel externally on compiler and AI systems.

The role involves mixed-signal design engineering focusing on timing analysis, circuit design using Cadence ADE, and verification methodologies.