Teams at Positron AI

Lead synthesis, timing convergence, and implementation readiness for AI accelerators. Own synthesis flows, SDC constraints, timing closure, physical-aware optimization, vendor coordination, and apply automation/AI to improve QoR and timing debug across multi-million-gate designs.

Lead physical implementation of AI accelerator ASICs from floorplanning through tapeout. Drive placement, CTS, P&R, signal/IR/EM closure, signoff, and methodology development. Partner with RTL, synthesis, DFT, package, and backend teams to deliver timing, power, area, congestion, and yield targets, and apply AI techniques to optimize QoR.

Lead architecture and performance exploration for next-generation AI inference accelerators. Build analytical models and simulation frameworks, define subsystem interfaces and roadmaps, and drive hardware/software co-design with compiler, runtime, ML, and silicon teams to optimize latency, throughput, memory, interconnects, power, and cost for evolving LLMs and transformer-based workloads.