Teams at Positron AI

Lead pre-silicon emulation strategy for a next-generation AI inference ASIC using Cadence Palladium. Architect multi-rack models, enable software left-shift via hybrid emulation, verify high-speed interfaces and memory hierarchies, perform power/performance analysis, and collaborate with RTL, DV, software teams and Cadence R&D to ensure silicon readiness.

Lead synthesis, timing convergence, and implementation readiness for AI accelerators. Own synthesis flows, SDC constraints, timing closure, physical-aware optimization, vendor coordination, and apply automation/AI to improve QoR and timing debug across multi-million-gate designs.

Lead physical implementation of AI accelerator ASICs from floorplanning through tapeout. Drive placement, CTS, P&R, signal/IR/EM closure, signoff, and methodology development. Partner with RTL, synthesis, DFT, package, and backend teams to deliver timing, power, area, congestion, and yield targets, and apply AI techniques to optimize QoR.