Teams at Positron AI

Lead power architecture, modeling, optimization, and verification for AI accelerators. Develop lifecycle power models, drive low-power techniques (clock/power gating, voltage islands), own UPF/CPF flows and power-aware verification, partner with cross-functional teams on power integrity and silicon validation, and apply AI tools to improve power analysis and anomaly detection.

Own synthesis, timing closure, constraint development, and implementation readiness for ASIC accelerator partitions. Execute Cadence Genus or Synopsys Design Compiler flows, develop SDC and MMMC environments, optimize timing, area, power, and congestion, and collaborate with RTL, verification, DFT, physical design, and backend teams. Improve synthesis methodology, analyze QoR and timing bottlenecks, support vendor partners, and apply AI tools to engineering automation and report analysis.

Leads microarchitecture, RTL implementation, and signoff for complex IP blocks and subsystems in AI inference ASICs and SoCs. Owns PPA optimization, interface and memory integration, lint, CDC/RDC, DFT, synthesis, and timing closure. Collaborates with architecture, verification, physical design, and vendors; develops design methodologies and automation; supports silicon bring-up and customer engagements; and mentors junior engineers while driving technical decisions.