Teams at SiFive

Improve and debug the RISC-V Linux kernel for high core-count server systems. Engage with upstream Linux and OpenSBI communities to post and review patches. Debug complex software and hardware CPU/SoC issues in emulation and FPGA platforms. Collaborate with system software, validation teams, CPU architects, and RTL engineers to advance core and system designs.

Architect and implement software and firmware for confidential computing on RISC-V/Silicon platforms. Collaborate with CPU/SoC/security teams, implement TEEs, virtualization and peripheral security solutions, write and review hardware/software specifications, and engage customers, partners, and standards bodies to drive platform security.