Top Tech Jobs & Startup Jobs in Calgary

Design and develop RFICs and mixed-signal ASICs using Cadence Virtuoso and Spectre RF. Build analog models and verification methodologies, create and execute pre/post-silicon test plans, trade off noise/linearity/power, support lab integration and troubleshooting, resolve layout and timing issues, collaborate with systems/firmware/architecture teams, and adopt AI-based methods across design, simulation, verification, characterization, and manufacturing.

Lead design and development of modem PHY IP for Terawave ASIC and prototypes. Translate algorithms into hardware architectures, build bit-accurate models, perform trade studies, define interfaces, support FPGA/silicon bring-up, collaborate with systems/ASIC/RF/verification teams, and analyze simulation/emulation/lab/silicon data to improve PHY performance and validation.

Lead verification of modem PHY IP: define strategies, build block/subsystem verification environments, create testbenches and coverage, correlate RTL with reference models, debug RTL and integration issues, support emulation/FPGA/prototyping and post-silicon debug, and drive regression automation and CI for high-throughput wireless ASIC platforms.

Lead DFX strategy for mechanical systems from concept to high-rate production. Drive DFM/DFA/DFR/DFC, tolerance analysis, GD&T, DOE, NPI, factory automation, failure analysis, and supplier readiness. Recruit and grow a global DFX team, establish assembly processes across multiple disciplines, and define DFX review gates and metrics to improve yield, reliability, and cost.

Design and develop mechanical hardware for the TeraWave satellite constellation and ground systems. Perform structural and thermal analyses, create CAD models/drawings/BOMs, support integration and environmental testing, apply GD&T, lead design reviews, mitigate risks, and collaborate with systems, electrical, manufacturing teams and suppliers.

Lead end-to-end hardware architecture for a phased-array satellite user terminal: define system block diagrams, select SoCs and high-speed components, resolve RF/electrical/mechanical interfaces, design power/thermal systems for beamforming, drive manufacturability with CMs, and establish validation and global compliance (FCC/CE/ETSI).

Lead design and development of user terminal hardware for a high-capacity satellite network. Integrate high-speed digital logic with phased-array antennas, design HDI PCBs and power delivery, route high-speed buses (PCIe/Ethernet/MIPI/SerDes), perform EMI/noise simulations, and own hardware bring-up, debugging, and system-level testing through product lifecycle.

Lead design and implementation of a custom MAC layer for a satellite constellation. Develop TDMA/DAMA schedulers, ARQ/AMC, handover logic, and optimize interfaces to high-speed packet engines (DPDK/VPP). Collaborate with PHY and network architects, drive MAC architecture decisions, and lead protocol development from simulation through hardware integration and field testing.

Lead design, simulation, fabrication, testing, and integration of high-performance phased-array and reflector antenna systems (Q/V/E-band) for a LEO/MEO satellite constellation. Own EM simulations, prototype development, anechoic chamber measurements, environmental qualification, and cross-discipline collaboration from concept through production readiness.

Lead the technical vision for product integrity across reliability, thermal, structural, materials, and qualification. Pioneer physics-of-failure methods, predictive reliability and AI-driven engineering, define testing/validation frameworks, mentor technical leaders, and align cross-disciplinary teams to ensure hardware survives launch and long-duration space deployment.