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The role involves leading the physical design of ASICs, overseeing all phases from RTL to GDSII, and enhancing design methodologies.

As a Verification Engineer, you will lead the verification of Serdes by developing AMS SystemVerilog models, collaborating with the design team, and ensuring model quality.

As a Digital Design Engineer at Eliyan, you will design and develop Ethernet PCS/PMA IPs, optimize digital designs, and collaborate on high-performance products.

As a Staff Digital Verification Engineer, develop verification plans, maintain test environments, and ensure compliance with Ethernet standards while leading junior engineers.

Lead and scale a design verification team for PHY and controller products. Define verification strategy and methodology (UVM, AMS, formal), drive verification planning and execution across link layer, PCS, PMA, and FEC, integrate analog models into digital flows, manage tapeout verification milestones, improve verification infrastructure and CI/CD, ensure standards compliance, and oversee vendor VIPs and firmware co-simulation for tapeout readiness.