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Lead and execute post-silicon functional validation for SerDes IP: develop validation strategies, design test plans and infrastructure, debug mixed-signal issues, perform root-cause analysis, document results, and collaborate with architecture, design, board, platform, and manufacturing teams to optimize validation and failure resolution.

Lead and scale Intel's compiler strategy and teams, driving multi-year direction for MLIR/LLVM-based compilers, AI/ML optimizations, and heterogeneous CPU/GPU/accelerator toolchains. Influence architecture and cross-functional roadmaps, deliver large cross-organizational programs, contribute to open-source standards, and represent Intel externally on compiler and AI systems.

The role involves mixed-signal design engineering focusing on timing analysis, circuit design using Cadence ADE, and verification methodologies.

Validate SerDes technologies, ensure mixed signal designs meet reliability and performance standards, drive innovation and collaborate on validation strategies.

The Modeling Development Engineer will integrate and validate software for microcontroller firmware and silicon models, leveraging expertise in silicon design and modeling development practices.

Lead design and validation of analog circuits for high-speed SerDes applications, guiding junior engineers, and collaborating across functions. Requires extensive experience in analog/mixed-signal design.

Design and develop analog circuits for high-speed SerDes applications, optimizing performance, testing designs, and mentoring engineers. Collaborate across teams to ensure designs meet specifications and drive technical direction.

The Senior Verification Engineer will lead ASIC design verification efforts, develop verification strategies, create test plans, and mentor junior engineers while ensuring coverage compliance.